The integrated circuit (IC) design is more challenging when semiconductor technologies are continually progressing to smaller feature sizes. The performance of an integrated circuit is seriously influenced by shape and sizes of various features in the IC design. During a lithography process, a feature defined on a mask is deformed due to proximity effect. To enhance the imaging effect when a design pattern is transferred to a semiconductor wafer, optical proximity correction (OPC) is indispensable. The design pattern is adjusted to generate an image on the wafer with improved resolution.
When electron-beam lithography is used to pattern a semiconductor wafer, corresponding proximity correction is implemented for enhanced resolution. However, in the existing method, there are still critical dimension (CD) variations among patterns with different pattern densities.
Therefore, what is needed is a method for proximity correction and lithography process to pattern wafers to reduce the CD variations.